Before describing the present invention, it will serve well to discuss some of the prior art in the area of signal sample acquisition and the immediate high-speed memory that serves it. As will be seen from the following discussion, part of the art of high speed data acquisition is in putting the acquisition memory as close to the raw input signal as possible, while taking care to preserve the sample integrity and present a high input impedance. The latter particularly includes minimizing the capacitive loading of the input signal.
U.S. Pat. No. 4,271,488 to Saxe for "High-Speed Acquisition System Employing An Analog Memory Matrix", hereby incorporated by reference, describes an acquisition system employing an analog memory matrix of sample-hold elements arranged in N.times.M rows and columns and connected to an analog signal bus. This memory may be written to very fast, and then read out at a more leisurely pace. It has therefore come to be known as a FISO, or "fast-in, slow-out" memory.
U.S. Pat. No. 4,648,072 to Hayes et al. for "High-Speed Data Acquisition Utilizing Multiplex Charge Transfer Devices", hereby incorporated by reference, describes two-phase charge coupled device (CCD) based acquisition memory. The two memories use opposite phases of the acquisition clock signal to demultiplex sample data from a single input line to achieve a doubling of acquisition speed. Each CCD memory has a delay line input, parallel internal structure, and a serial output. This is known as a serial-parallel-serial structure, or "SPS". See also, U.S. Pat. No. 4,951,302 to Peter et al. for "Charge-Coupled Device Shift Register", hereby incorporated by reference. And, further use of the CCD memory in an SPS layout is described in U.S. Pat. No. 5,200,983 for Kogan for "FISO Analog Signal Acquisition System Employing CCD Array Storage".
U.S. Pat. No. 4,922,452 to Larsen et al. for "10 Gigasample/sec Two-stage Analog Storage Integrated Circuit For Transient Digitizing and Imaging Oscillography", hereby incorporated by reference, describes an acquisition system employing a two-stage sampling cell at each x-y location. The first stage, or capture section, has a very small capacitor to collect samples at very high speed with minimum loading effect. When all of the first capture sections have data, a transfer gate is briefly opened to transfer the captured and buffered to the second, or storage, stage of the memory. The storage stage employs larger capacitors appropriate for storing samples for a longer period of time.
U.S. Pat. No. 5,144,525 to Saxe et al. for "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference, describes various ways to produce a high speed sampling strobe for sampling data into FISO-type memories. The total time used to generate multiple strobes has to be made equal to the time required to fill a single row with data.
Then, access to that row is shut off, access to the next row is turned on, and another set of multiple strobes are used to put data into that next row.
U.S. Pat. No. 5,526,301 to Saxe for "High-Speed Analog Acquisition Including Signal Processing", hereby incorporated by reference, describes a system with a high-speed sequential sampling input circuit whose outputs are processed in parallel by multiple layers of signal processing units with a set of selectable functions. These selectable functions include: greater of the inputs as the output, the sum of two analog input levels as the output, either input multiplied by a variable as the output. The latter function can be used to selectively decimate the input samples and "steer" particular inputs to the final output layer of signal processing units. The use of variable multiplication factors allows this circuitry to be used as a finite impulse response filter.
U.S. Pat. No. 5,406,507 to Knierim et al. for "Reduced Input Capacitance Analog Storage Array", hereby incorporated by reference, describes a DRAM-like two-dimensional array of capacitors in which each cell communicates with a column line through x-y addressing devices, and each column communicates with the input line through a column separation device.
Over the years, the importance of record length as a competitive factor in oscillography has increased, making it more and more important to achieve depth of acquisition, as well as signal integrity and high input impedance. The invention described below therefore has as one of its objectives the attainment of very long record lengths, while maintaining the quality of other aspects of the acquisition process.
As is described in U.S. Pat. No. 4,271,488 to Saxe for "High-Speed Acquisition System Employing an Analog Memory Matrix" and U.S. Pat. No. 5,144,525 to Saxe et al. for "Analog Acquisition System Including a High Speed Timing Generator", values are read into the sample cells by charging them to a voltage level, V.sub.CAP, proportional to the voltage value of the input signal at that point in time. Refer to FIGS. 1 and 2. The capacitors in the storage cells then hold a charge, Q.sub.CAP, that is the product of the sampled voltages, V.sub.CAP, and the size of the capacitors, C.sub.CAP, in the storage cells. The elements of the storage cells are desirably made to be as uniform as possible from cell to cell, so as to minimize any distortion that they would otherwise create in the acquired data.
Acquisition Cell 1, Acquisition Cell 2, and all the other acquisition cells, comprise a strobe controlled switch, an acquisition capacitor, and an output buffer amplifier. (See, for example, U.S. Pat. No. 5,144,525, FIG. 20, elements 110 and 116.) The switch is briefly closed by a strobe signal, thereby temporarily connecting the analog signal line to the acquisition capacitor. The output buffer amplifier then presents a voltage that is representative of the charge on the acquisition capacitor to a column of memory cells in the array of memory cells.
In the read-out cycle used with such an acquisition memory, typically all of the column enable signals are pre-charged to the power supply voltage, V.sub.DD, while the row enable signal remains inactive. The charge on each column is then Q.sub.COL, which is the product of the column's capacitance, C.sub.COL, and the power supply voltage, V.sub.DD. As each row enable signal is then sequentially activated and deactivated, it connects the storage cell charge, Q.sub.CAP, and the column charge, Q.sub.COL, to each other. The common voltage that results, V.sub.COM, is equal to the sum of the charges, Q.sub.CAP and Q.sub.COL, divided by the sum of the capacitances C.sub.CAP and C.sub.COL. ##EQU1## where, [C.sub.COL .times.V.sub.DD ]/[C.sub.CAP +C.sub.COL ] is a portion of the V.sub.COM signal that is determined by the cell and column geometries and power supply voltage. In operation, this part of the V.sub.COM values is constant and therefore needs to be subtracted from each of the V.sub.COM values at some point in the process.
The other part of the V.sub.COM values, [C.sub.CAP .times.V.sub.CAP ]/[C.sub.CAP +C.sub.COL ], which can be rearranged as V.sub.CAP /[1+C.sub.COL /C.sub.CAP ], is proportional to V.sub.CAP and inversely proportional to the ratio C.sub.COL /C.sub.CAP. Increasing the length of rows, to increase array size, has the undesirable effect of increasing C.sub.COL, and thereby decreasing the size of the useful value compared with the constant part. Since the useful part of the signal is obtained by subtracting the common part from the total, this has an adverse effect on the signal-to-noise ratio and linearity, or overall signal fidelity.